The L4-embedded microkernel created by CSIRO’s Data61 is already used in billions of mobile devices worldwide to enhance security. Now, a secure version of L4 — called seL4 — is redefining operating-system security and setting a new standard for computer security.

Data61 has today released an initial version of seL4 for RISC-V (pronounced risk-five), a free and open Instruction Set Architecture (ISA*) enabling a new era of processor innovation through open standard collaboration.

Future versions of the seL4 microkernel will fully support the RISC-V architecture. The RISC-V Foundation has significant backing from over 100 members including major industry players such as IBM, Google, Microsemi, Qualcomm, Samsung, Western Digital and many more.

CSIRO has joined the RISC-V Foundation to participate in ongoing work and contribute to the RISC-V ISA specification with the aim of enhancing overall security.  

Professor Gernot Heiser, Chief Research Scientist for Trustworthy Systems at CSIRO’s Data61, will represent the organisation on the RISC-V Foundation’s security task groups to help prevent a repeat of security debacles such as Meltdown and Spectre which affected billions of devices globally.  

Professor Heiser said that the new architecture can liberate the IT industry from design errors of the past.  

“RISC-V, through its openness and greenfield design, provides an opportunity for re-thinking the hardware-software stack,” Professor Heiser said. 

“The open architecture, which is designed by leading architects and has strong industry support, is an ideal platform for our open-source seL4 system.

"We anticipate the combination of seL4 and RISC-V to provide a compelling security solution for the next-generation Internet of Things and cyber-physical systems.”  

Rick O’Connor, Executive Director of the RISC-V Foundation, welcomed CSIRO as a member.  

“We are excited to see seL4 added to the RISC-V ecosystem,” Mr O’Connor said.

“Data61’s visionary team of operating system security and verification experts will help ensure RISC-V based systems will meet future cybersecurity challenges.”  

Dr June Andronick, Leader of Data61’s Trustworthy Systems research group, said: "We see RISC-V as one of the most exciting developments in computer systems right now, and are pleased to collaborate with other members of the RISC-V Foundation on changing the game in computer security."  

Adrian Turner, CEO at CSIRO’s Data61, said cyber security is a core focus for the organisation.  

“The seL4 microkernel is one of our flagship achievements that is being designed into safety- and security-critical systems around the world,” Mr Turner said.

“Our involvement with the RISC-V Foundation will further increase the international impact of Data61’s research and development.”  

For more information on RISC-V, visit: riscv.org

*An instruction set architecture (ISA) is an abstract model of a computer, and serves as the interface between software and hardware. An ISA defines everything a machine language programmer needs to know in order to program a computer or piece of software.

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